This invention relates to integrated circuit semiconductor transducer structures and more particularly to a binary balancing apparatus for providing compensation of such a transducer.
The prior art is replete with a large number of patents and literature disclosing transducers which are fabricated from piezoresistive elements, which elements may be integrally diffused within a diaphragm of semiconducting material such as silicon. Such devices are fabricated using solid state techniques which basically involve the diffusion or deposition of a force sensitive arrangement of piezoresistors on a semiconductor diaphragm. The integral silicon transducers are conventionally formed in a four active arm Wheatstone bridge configuration, which bridge assembly provides an output proportional to pressure and/or deflection. The stress sensors or piezoresistors are typically arranged so that two elements of the four are subjected to tension and two are subjected to compression. This type of arrangement has been referred to in the prior art as an integral or integrated transducer and the terminology is used to denote the fact that the piezoresistive sensing elements are actually deposited, diffused or otherwise formed on a semiconductor substrate employing fabrication techniques used in integrated circuit technology.
Based on the above noted technology, such transducers have been formed which are extremely small, rugged and relatively economical. Examples of typical structures which possess many of the attributes indicated above can be had by referring to U.S. Pat. No. 4,016,644 entitled METHODS OF FABRICATING LOW PRESSURE SILICON TRANSDUCERS issued on Apr. 12, 1977 to A. D. Kurtz, U.S. Pat. No. 3,935,634 entitled METHODS OF FABRICATING INTEGRATED TRANSDUCER ASSEMBLIES issued on Feb. 3, 1976 to A. D. Kurtz et al., U.S. Pat. No. 3,900,811 issued on Aug. 19, 1975 to A. D. Kurtz et al., U.S. Pat. No. 3,873,956 entitled INTEGRATED TRANSDUCER ASSEMBLIES issued on Mar. 25, 1975 to A. D. Kurtz et al. All of the above patents are assigned to the assignee herein and in general, involve and describe integrated transducer structures and techniques for fabricating the same.
The transducer configuration as a half bridge array or a full Wheatstone bridge array is widely employed and is an extremely typical arrangement. In such transducers it is necessary to compensate the transducer in regard to temperature variation as well as balancing the transducer for optimum operation. Essentially, temperature compensation of a transducer is well known and involves compensating circuitry which provides a compensating effect for variations of the semiconductor transducer over a wide range of temperature operation. In regard to such techniques, the prior art has proposed many different approaches. For example, U.S. Pat. No. 3,886,799 entitled SEMICONDUCTOR PRESSURE TRANSDUCER EMPLOYING TEMPERATURE COMPENSATION CIRCUITS AND NOVEL HEATER CIRCUITRY issued on June 3, 1975 to Billette et al. and assigned to the National Semiconductor Corporation shows one approach. This patent describes a voltage regulator which is coupled to a Wheatstone bridge including a Zener diode and associated transistor circuitry for compensating a bridge and the voltage supply over a wide range of temperatures. Other patents such as U.S. Pat. No. 3,245,252 entitled TEMPERATURE COMPENSATED SEMICONDUCTOR STRAIN GAGE UNIT issued on Apr. 12, 1966 to D. J. First et al. disclose an arrangement of series and shunt resistors which essentially are used to provide temperature compensation for the bridge configuration. This patent is relatively typical of the prior art technique of performing zero shift and zero balance.
For purposes of explanation, zero shift compensation refers to compensation of the transducer null or zero pressure reading as a function of temperature. Zero balance is the compensation of a transducer for zero pressure applied to the transducer. For example, a transducer may be temperature balanced and hence, its zero output change will be relatively small as the temperature changes or varies. However, the transducer may still provide an undesired voltage level when no pressure is being applied to the active portion of the diaphragm. This also must be compensated for, as for example, it is desirable to have the transducer indicate an approximately zero voltage output for no applied pressure at all temperatures over its operating range. In present technology, due to the fact that the piezoresistors which form the bridge are all deposited simultaneously by the same technique on the same diaphragm, these sensors, for practical purposes, perform very well over wide temperature ranges. Due to the fact that the resistors are also positioned in close proximity and deposited by the same technique, they are relatively temperature matched and the reading at zero pressure is relatively constant with temperature variations.
It is relatively easy to zero balance an integral semiconductor bridge by employing suitable resistors, which are often, according to prior art, temperature insensitive resistances. Such resistors do not normally vary resistance value as a function of temperature or if temperature sensitive resistors are used for balance, their temperature characteristics are not identical to those of the bridge elements. Moreover, temperature gradients often exist between the location of the bridge elements and a suitable location for balance resistors. Thus, the inclusion of a balance resistor can, in general, be expected to cause an unwanted change in zero balance with temperature because it changes the temperature characteristics of the bridge element to which it is added. This effect can be overcome by adding several resistors to the bridge network, but this is an additional complication and moreover, these resistors can contribute to a lack of zero stability in the transducer. Present technology allows for the manufacture of a semiconductor transducer which exhibits essentially no zero shift and excellent zero stability and repeatability. Thus, the addition of compensating resistors only serves to degrade transducer performance. Hence, adjusting for both zero balance and temperature shift is extremely complicated and difficult to implement and compromises the temperature performance.
Other factors which are peculiar to integrated circuit transducer configurations make the balancing of such units even more difficult by the use of discrete components as those employed in the prior art and hence, the entire procedure become extremely difficult and time consuming. In fact, such balancing procedures are accommodated by computer aided programs, which programs implement a complete circuit analysis for a given resistive array for each individual transducer to arrive at specified values for a resistive arrangement such as that arrangement depicted in U.S. Pat. No. 3,245,252.
It is therefore an object of this invention to provide a simple and reliable balancing configuration for an integrated circuit transducer, which compensating arrangement serves to provide zero balance extremely efficiently, thus circumventing and avoiding many of the above noted problems.